Many circuits drive a capacitive load in response to an input signal. Often the circuits are designed to drive the capacitive load to a certain charge or voltage while in a drive mode. Once the capacitive load reaches the charge or voltage the circuit enters a mode where the charge or voltage is maintained. Such a mode is sometimes referred to as the steady-state mode because the charge or voltage is essentially constant. In many such circuits it is desirable that the voltage or charge on the capacitive load accurately represent the steady-state mode. For instance, one such drive circuit is an amplifier circuit in which the charge or voltage at the steady-state mode represents an amplified input signal.
After the circuit begins to drive the capacitive load, the time necessary to guarantee that the circuit has reached a steady-state mode is sometimes referred to as the settling time. This time is relevant to both the speed of the circuit and the power dissipation of the device. In some applications the settling time can be reduced by increasing the drive strength of the circuit, however, this can result in increased power dissipation and can also cause ringing of the charge or voltage on the load. As devices decrease in size (e.g., portable devices) and increase in accuracy, the competing desires for increased accuracy and decreased power dissipation become more difficult to accomplish.
Particular examples of driver circuits are used in switched-capacitor circuits, such as analog to digital converters (ADCs). Two specific examples of ADCs are cyclic and pipeline, both of which have a first stage that produces a digital representation of the step input signal having a certain amount of precision. This digital representation is converted back to an analog signal and subtracted from the original input signal. The resulting signal represents a portion of the signal that was not accounted for by the precision of the digital representation. The resulting signal is applied to a driver circuit that often acts as an amplifier. The driver circuit drives a capacitive load that can be used to generate a digital representation having a higher amount of precision relative to the first amount of precision. In a cyclic ADC, the capacitive load is used as an input to the original ADC stage. In a pipeline ADC, the capacitive load is used as an input to a second ADC stage. For either type of ADC, the process can be repeated until the desired precision is obtained.
ADCs have increasing need for increased performance and reduced power dissipation as applications become both more complex and smaller in size. Because the output of the first stage can be amplified many times, errors in the first stage are also amplified. Thus, current applications using ADCs allow the driver circuit sufficient active time in order to guarantee that the driver circuit has reached the steady-state mode. Moreover, in order to reduce the settling time, ADCs use strong driver circuits that require large amounts of power. One reason for using strong driver circuits is that it is often undesirable to decrease the capacitive load as the decrease can result in increased errors due to process variations and electronic noise.
These and other issues have presented challenges to the implementation and design of driver circuits, including those involving switched-capacitor circuits and similar applications. Accordingly, there is a need for a capacitive drive circuit that provides increased accuracy or reduced power consumption.